By Topic

Suppression of the boron penetration induced Si/SiO/sub 2/ interface degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Shye Lin Wu ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chung Len Lee ; Tan Fu Lei ; Chen, J.F.
more authors

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO/sub 2/ interface. An atomically flat Si/SiO/sub 2/ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p/sup +/ poly-Si gate MOS devices even with the annealing temperature as high as 1000/spl deg/C.<>

Published in:

Electron Device Letters, IEEE  (Volume:15 ,  Issue: 5 )