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Optimal balancing of acyclic and cyclic data flow graphs in high level architectural synthesis environment

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2 Author(s)
A. Antola ; Dipartimento di Inf. e Sistemistica, Pavia Univ., Italy ; F. Distante

In this paper, data flow graphs are used to represent the algorithmic description of a problem and serve as the starting description for high level architectural synthesis process. No assumption is made on the class of DFGs considered (i.e. iterative or general) thus allowing the description of any algorithm. Balancing of DFGs where nodes represent computational activities whose exchange of information is not self synchronised is a convenient way to raise the throughput of the graph (architecture). This paper presents a methodology that allows balancing acyclic and cyclic data flow graphs optimizing both latency and throughput

Published in:

Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on

Date of Conference:

19-21 Jan 1994