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An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors

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2 Author(s)
Chin-Chien Sha ; Dept. of Electr. & Comput. Eng., Missouri Univ., Columbia, MO, USA ; Leavene, R.W.

An algorithm is proposed to maintain fault tolerance for a highly reliable FFT processor, even after the processor has been reconfigured (by detecting a single fault). It proves that the concurrent error detection (CED) scheme using: a redundant stage of decimation in frequency FFT (DIF-FFT) butterflies as a decoder can detect all the faults theoretically. This CED scheme and the modification of the standard DIF-FFT processor as a recirculated shuffle exchange will also alleviate the difficulty of reconfiguration and will provide the ability of some degradation in performance in the presence of more than one fault in the processor

Published in:

VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on

Date of Conference:

4-5 Mar 1994