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An evaluation of multiprocessor cache coherence based on virtual memory support

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2 Author(s)
Petersen, K. ; Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA ; Li, K.

This paper presents an evaluation of the impact of several architectural parameters on the performance of virtual memory (VM) based cache coherence schemes for shared-memory multiprocessors. The VM-based cache coherence schemes use the traditional VM translation hardware on each processor to detect memory access attempts that might leave caches incoherent, and maintain coherence through VM-level system software. The implementation of this class of coherence schemes is flexible and economical: it allows different consistency models, requires no special hardware for multiprocessor cache coherence, and supports arbitrary interconnection networks. We used trace-driven simulations to evaluate the effect of the architectural parameters on the performance of the VM-based schemes. These parameters include VM page sizes. Write-back and write-through caches, memory access latencies, bus and crossbar interconnections, and different cache sizes. Our results show that VM-based cache coherence can be a very practical approach for building shared-memory multiprocessors

Published in:

Parallel Processing Symposium, 1994. Proceedings., Eighth International

Date of Conference:

26-29 Apr 1994