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Latency hiding in message-passing architectures

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3 Author(s)
Bruening, U. ; GMD Inst. for Comput. Archit. and Software Technol., Berlin, Germany ; Giloi, W.K. ; Schroeder-Preikschat, W.

The paper demonstrates the advantages of having two processors in the node of a distributed memory architecture, one for computation and one for communication. The architecture of such a dual-processor node is discussed. To exploit fully the potential for parallel execution of computation threads and communication threads, a novel, compiler-optimized IPC mechanism allows for an unbuffered no-wait send and a prefetched receive without the danger of semantics violation. It is shown how an optimized parallel operating system can be constructed such that the application processor's involvement in communication is kept to a minimum while the utilization of both processors is maximized. The MANNA implementation results in an effective message start-up latency of only 1...4 microseconds. It is also shown how the dual-processor node is utilized to efficiently realize virtual shared memory

Published in:

Parallel Processing Symposium, 1994. Proceedings., Eighth International

Date of Conference:

26-29 Apr 1994