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Impact of sharing-based thread placement on multithreaded architectures

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2 Author(s)
R. Thekkath ; Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA ; S. J. Eggers

Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interference and degrade overall performance. One technique to reduce the interconnect traffic is to co-locate threads that share data on the same processor. Multiple threads sharing in the cache should reduce compulsory and invalidation misses, thereby improving execution rime. To test this hypothesis, the authors compared a variety of thread placement algorithms via trace-driven simulation of fourteen coarse- and medium-grain parallel applications on several multithreaded architectures. The results contradict the hypothesis. Rather than decreasing, compulsory and invalidation misses remained neatly constant across all placement algorithms, for all processor configurations, even with an infinite cache. That is, sharing-based-placement had no (positive) effect on execution time. Instead load balancing was the critical factor that affected performance. The results were due to one or both of the following reasons: (1) the sequential and uniform access of shared data by the application's threads and (2) the insignificant number of data references that require interconnect access, relative to the total number of instructions

Published in:

Computer Architecture, 1994., Proceedings the 21st Annual International Symposium on

Date of Conference:

18-21 Apr 1994