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The Stanford FLASH multiprocessor

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13 Author(s)
Kuskin, J. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Ofelt, D. ; Heinrich, M. ; Heinlein, J.
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The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message passing, while minimizing both hardware and software overhead. Each node in FLASH contains a microprocessor, a portion of the machine's global memory, a port to the interconnection network, The MAGIC chip handles all communication both within the node and among nodes, using hardwired data paths for efficient data movement and a programmable processor optimized for executing protocol operations. The use of the protocol processor makes FLASH very flexible-it can support a variety of different communication mechanisms-and simplifies the design and implementation. This paper presents the architecture of FLASH and MAGIC, and discusses the base cache-coherence and message-passing protocols. Latency and occupancy numbers, which are derived from our system-level simulator and our Verilog code, are given for several common protocol operations. The paper also describes our software strategy and FLASH's current status

Published in:

Computer Architecture, 1994., Proceedings the 21st Annual International Symposium on

Date of Conference:

18-21 Apr 1994