By Topic

Partial arithmetic-algorithms and architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
J. Starzyk ; Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA ; M. SenthilKumar

This paper proposes a new concept in computer arithmetic and delineates algorithms for addition, subtraction and multiplication. The proposed architecture is capable of performing additions in constant time and multiplication, in time less than in the best known architectures. The internal representation of numbers is called “a+b” and requires two memory words. The paper also discusses special coding multiplication and organization of the multiplier for VLSI implementation

Published in:

System Theory, 1994., Proceedings of the 26th Southeastern Symposium on

Date of Conference:

20-22 Mar 1994