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A digital neural network architecture using random pulse trains

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2 Author(s)
Erten, G. ; Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA, USA ; Goodman, R.M.

A digital neural network architecture generating and processing random pulse trains is described, along with its unique advantages over existing comparable systems. In addition, test results from the VLSI implementation of its multiplication scheme are presented. As can be inferred from the test plots, the circuit is robust and quite accurate over a wide range of clock frequencies. This robustness is believed to be congenial to the exploration of novel training algorithms in such a system. One could, by reducing the time constant of the time averaging circuit and thus averaging the pulse train over a smaller number of clock cycles, get significant variations in output activity for the same input. The use of the statistical properties of these variations among computing units could have novel implications in weight update decisions during training

Published in:

Neural Networks, 1992. IJCNN., International Joint Conference on  (Volume:1 )

Date of Conference:

7-11 Jun 1992