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ALADIN: a multilevel testability analyzer for VLSI system design

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6 Author(s)
Bombana, M. ; Italtel Soc. Italiana Telecommun. SpA, Milan, Italy ; Buonanno, G. ; Cavalloro, P. ; Ferrandi, F.
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In order to cope with tomorrow's challenges in the microelectronic market, the reliability of the first phases of the design process must be improved. The possibility of applying techniques for testability analysis at these abstract design levels can considerably help in achieving this goal, reducing at the same time system design costs. In this paper we introduce a novel approach for the application of functional testability at system design level and demonstrate the possibility of its application in an industrial environment. Testability conditions referring to both regular and irregular topologies have been defined, formalized and inserted into the knowledge base of the expert system, ALADIN. This tool operates as a testability analyzer able to identify critical areas for testability in designs whose functional modules and local interconnections are known and described in standard VHDL. The architecture of the tool has been defined in order to satisfy the users' requirements including the integrability into a standard CAD design flow through standard I/O interfaces. Then its application to both a regular and an irregular topology are presented in order to show on real examples which testability conditions apply, and how the tool operates in order to reach the testability assessment. From these industrial case studies, figures of merit are derived from which it is possible to evaluate the importance of the application of such a methodology to system level design.<>

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:2 ,  Issue: 2 )