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FFT computation with systolic arrays, a new architecture

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1 Author(s)
V. Boriakoff ; Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA

The use of the Cooley-Tukey algorithm for computing the 1-d FFT lends itself to a particular matrix factorization which suggests direct implementation by linearly-connected systolic arrays. Here we present a new systolic architecture that embodies this algorithm. This implementation requires a smaller number of processors and a smaller number of memory cells than other recent implementations, as well as having all the advantages of systolic arrays. For the implementation of the decimation-in-frequency case, word-serial data input allows continuous real-time operation without the need of a serial-to-parallel conversion device. No control or data stream switching is necessary. Computer simulation of this architecture was done in the context of a 1024 point DFT with a fixed point processor, and CMOS processor implementation has started

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:41 ,  Issue: 4 )