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A 1.5 V BiCMOS dynamic logic circuit using a “BiPMOS pull-down” structure for VLSI implementation of full adders

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5 Author(s)
J. B. Kuo ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; S. S. Chen ; C. S. Chiang ; K. W. Su
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This paper presents a 1.5 V BiCMOS dynamic logic circuit using a “BiPMOS pull-down” structure, which is free from race problems, for VLSI implementation of full adders. Using the 1.5 V BiCMOS dynamic logic circuit, a 16-bit full adder circuit, which is composed of half adders and a carry look-ahead circuit, shows a 1.7 times improvement in speed as compared to the CMOS static one

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IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications  (Volume:41 ,  Issue: 4 )