A 1.5 V BiCMOS dynamic logic circuit using a "BiPMOS pull-down" structure for VLSI implementation of full adders

This paper presents a 1.5 V BiCMOS dynamic logic circuit using a "BiPMOS pull-down" structure, which is free from race problems, for VLSI implementation of full adders. Using the 1.5 V BiCMOS dynamic logic circuit, a 16-bit full adder circuit, which is composed of half adders and a carry look-ahead circuit, shows a 1.7 times improvement in speed as compared to the CMOS static one.<
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