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Embedding binary X-trees and pyramids in processor arrays with spanning buses

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2 Author(s)
Zicheng Guo ; Dept. of Electr. Eng., Louisiana Tech. Univ., Ruston, LA, USA ; R. G. Melhem

We study the problem of network embeddings in 2-D array architectures in which each row and column of processors are interconnected by a bus. These architectures are especially attractive if optical buses are used that allow simultaneous access by multiple processors through either wavelength division multiplexing or message pipelining, thus overcoming the bottlenecks caused by the exclusive access of buses. In particular, we define S-trees to include both binary X-trees and pyramids, and present two embeddings of X-trees into 2-D processor arrays with spanning buses. The first embedding has the property that all neighboring nodes in X-trees are mapped to the same bus in the target array, thus allowing any two neighbors in the embedded S-trees to communicate with each other in one routing step. The disadvantage of this embedding is its relatively high expansion cost. In contrast, the second embedding has an expansion cost approaching unity, but does not map all neighboring nodes in X-trees to the same bus. These embeddings allow all algorithms designed for binary trees, pyramids, as well as X-trees to be executed on the target arrays

Published in:

IEEE Transactions on Parallel and Distributed Systems  (Volume:5 ,  Issue: 6 )