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Estimating implementation bounds for real time DSP application specific circuits

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2 Author(s)
J. M. Rabaey ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; M. Potkonjak

This paper discusses techniques for estimating implementation bounds on computational resources and their role in the high-level synthesis process. Accurate estimations can be extremely useful in a multitude of synthesis operations, such as algorithm and architecture selection, design space search, module selection, transformations, allocation, assignment, and scheduling. Several techniques to efficiently estimate sharp minimum and maximum bounds on the resource requirements of a hardware implementation are discussed. The performance of the algorithms as well as their applications is analyzed using an extensive benchmark set. The proposed techniques have been implemented in the HYPER synthesis system

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:13 ,  Issue: 6 )