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An analog systolic neural processing architecture

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5 Author(s)
Moreno, J.M. ; Catalunya Polytech. Univ., Spain ; Castillo, F. ; Cabestany, J. ; Madrenas, J.
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Developed for the VLSI implementation of neural network models, our novel analog architecture adds flexibility and adaptability by incorporating digital processing capabilities. Its systolic-based architecture avoids static storage of analog values by transferring the activation values through the chip's processing units. This proposed combination of analog and digital technologies produces a densely packed, high-speed, scalable architecture, designed to easily accommodate learning capabilities.<>

Published in:

Micro, IEEE  (Volume:14 ,  Issue: 3 )

Date of Publication:

June 1994

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