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Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation

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5 Author(s)
K. N. Quader ; Dept. of Electr. Eng., California Univ., Berkeley, CA, USA ; Peng Fang ; J. T. Yue ; P. K. Ko
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Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the “zero crossing” effect caused by PMOSFET current enhancement. Saturation drain current, measured at Vgs=Vds=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ftrise and 10/ftfall, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively

Published in:

IEEE Transactions on Electron Devices  (Volume:41 ,  Issue: 5 )