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A concurrent error detection IC in 2-μm static CMOS logic

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3 Author(s)
Lo, J.-C. ; Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA ; Shih-Yao Sun ; Daly, J.C.

When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code disjoint (SCD) built-in current sensor (BICS). This chip was fabricated by MOSIS using 2 μm p-well CMOS technology. In chip tests, all implanted faults, including analog faults, were detected as expected. We also show that the self-exercising mechanism of the SCD BICS is indeed functioning properly. This is the first demonstration of a working static CMOS CED chip

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 5 )