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High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

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4 Author(s)
Ishii, K. ; Integrated Circuit Technol. Lab., NTT LSI Labs., Kanagawa, Japan ; Ichino, H. ; Kobayashi, Y. ; Yamaguchi, C.

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-μm photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mVp-p. An extremely high input sensitivity of 15 mVp-p and a wide phase margin of 260° at 10 Gb/s are achieved

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 5 )

Date of Publication:

May 1994

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