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The feasibility of using compression to increase memory system performance

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2 Author(s)
J. Wang ; Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA ; R. W. Quong

We investigate the feasibility of using instruction compression at some level in a multi-level memory hierarchy to increase memory system performance. Compression effectively increases the memory size and the line size reducing the miss rate at the expense of increased access latency due to decompression delays. We analytically evaluate the impact of compression on the average memory access time for various memory systems and compression approaches. Our results show the benefit of using compression is sensitive to the miss rates and miss penalties at the point of compression and to a lesser extent the amount of compression possible. For high performance workstations of today, compression already shows promise; as miss penalties increase in future, compression will only become more feasible

Published in:

Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1994., MASCOTS '94., Proceedings of the Second International Workshop on

Date of Conference:

31 Jan-2 Feb 1994