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Low power architecture design and compilation techniques for high-performance processors

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3 Author(s)
Ching-Long Su ; Adv. Comput. Archit. Lab., Univ. of Southern California, Los Angeles, CA, USA ; Chi-Ying Tsui ; A. M. Despain

Reducing switching activity would significantly reduce power consumption of a processor chip. The authors present two novel techniques, Gray code addressing and Cold scheduling, for reducing switching activity on high performance processors. They use Gray code which has only one-bit different in consecutive number for addressing. Due to locality of program execution, Gray code addressing can significantly reduce the number of bit switches. Experimental results show that for typical programs running on a RISC microprocessor, using Gray code addressing reduce the switching activity at the address lines by 30/spl sim/50% compared to using normal binary code addressing. Cold scheduling is a software method which schedules instructions in a way that switching activity is minimized. The authors carried out experiments with cold scheduling on the VLSI-BAM. Preliminary results show that switching activity in the control path is reduced by 20-30%.<>

Published in:

Compcon Spring '94, Digest of Papers.

Date of Conference:

Feb. 28 1994-March 4 1994