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Power constraint scheduling of tests

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3 Author(s)
R. M. Chou ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; K. K. Saluja ; V. D. Agrawal

This paper presents motivation for considering the power constraint in testing and gives a model-based formulation of the new test scheduling problem. Optimum test scheduling algorithms are presented for both equal and unequal test length cases under the power constraint. The algorithms consist of three basic steps. First, we find a complete set of time compatible tests with power dissipation information associated with each test. Second, from these tests, we extract the lists of power compatible tests. And finally, we use a minimum cover table approach to find the optimal scheduling of the tests

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994