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A methodology for architecture synthesis of cascaded IIR filters on TLU FPGAs

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3 Author(s)
Rathna, G.N. ; Dept. of Electr. Eng., Indian Inst. of Sci., Bangalore, India ; Nandy, S.K. ; Parthasarathy, K.

In this paper, we propose an architecture synthesis methodology to realize cascaded infinite impulse response (IIR) filter in table look up (TLU) field programmable gate arrays (FPGA). The synthesis procedure involves a systematic transformation of the dependance graph (DG) corresponding to the cascaded IIR filler to a pipelined fixed full size array (PFFSA). We offer an implementation of a cascaded 8th order IIR filters on Xilinx XC3090 FPGA devices

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994