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IDDQ detection of CMOS bridging faults by stuck-at fault tests

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3 Author(s)
S. Hwang ; Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA ; R. Rajsuman ; S. Davidson

Many of the physical defects in CMOS circuits such as bridging and transistor stuck-on faults are not guaranteed to be detected by logic testing. In this paper, we examine the detection efficiency of stuck-at tests in covering all possible bridging faults in IDDQ environment. We generate stuck-at fault test vectors for combinational and sequential benchmark circuits using standard ATPG programs. The circuits are simulated with these vectors and power supply current was monitored for bridging faults. A high current state in a faulty circuit is considered as an indicator of fault detection. The test results are given in terms of intra-transistor and gate-level bridging fault coverage. Our results show that stuck-at test vectors can be used very efficiently for IDDQ testing of bridging faults, and extra effort to generate specialized test vectors may be unnecessary

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994