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A test function architecture for interconnected finite state machines

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3 Author(s)
Kanjilal, S. ; Dept. of Comput. Sci., Rutgers Univ., New Brunswick, NJ, USA ; Chakradhar, S.T. ; Agrawal, V.D.

We propose a new test machine architecture as a cascade of small component test machines. A component test machine uses the same output symbols as the input symbols of the next test machine in the cascade. The output symbols of the last test machine are primary outputs of the circuit and the input symbols of the first test machine are the primary inputs of the circuit. For synthesizing an object machine, given as an interconnection of component machines, for testability, the components of the test machine are embedded one-by-one into the components of the object machine. This embedding may require at most one extra input for the entire circuit. Each composite component machine is separately synthesized. The test generation procedure has the same complexity as that for scan design. This architecture is also applicable to single finite state machine and large gate-level circuits through partitioning and resynthesis. Experimental results show the practicality of the approach

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994

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