By Topic

A VLSI architecture of an inverse discrete cosine transform

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
A. K. Bhattacharya ; AT&T Bell Labs., Murray Hill, NJ, USA ; S. S. Haider

The inverse discrete cosine transform (IDCT) is an important function in HDTV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the sequence of input coefficients and the output data, the rows and columns of the transform matrix can be reordered to build modular regularity which is suitable for VLSI implementation. Based on this technique, an architecture using only seven constant multipliers and only one 1 dimensional IDCT processor is presented

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994