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Parallel model evaluation for circuit simulation on the PACE multiprocessor

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4 Author(s)
Agrawal, P. ; AT&T Bell Labs., Murray Hill, NJ, USA ; Goil, S. ; Liu, S. ; Trotter, J.A.

Device model evaluation, an essential part of a circuit simulator, is a compute-intensive task. A multiprocessor-based circuit simulator that ignores the parallelization of model equation formulation (LOAD), and just parallelizes the solution (SOLVE) of the equations will seriously degrade the simulation performance. This paper describes methods of parallelizing the LOAD part of a circuit simulator on PACE (Parallel Architecture for Circuit Evaluation) a distributed memory multiprocessor designed at AT&T Bell Laboratories. This is integrated with the parallel SOLVE algorithms given in our earlier work. Load balancing and minimization of interprocessor communication are used as the primary objectives of the parallel LOAD heuristics studied. Performance results, using the prototype PACE system, on benchmark circuits show the feasibility of our approach

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994