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TITAC: design of a quasi-delay-insensitive microprocessor

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5 Author(s)
Nanya, T. ; Tokyo Inst. of Technol., Japan ; Ueno, Y. ; Kagotani, H. ; Kuwako, M.
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TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation.<>

Published in:

Design & Test of Computers, IEEE  (Volume:11 ,  Issue: 2 )