Cart (Loading....) | Create Account
Close category search window

Parallel implementation of the fast Fourier transform on two TMS320C25 digital signal processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Hen-Geul Yeh ; Dept. of Electr. Eng., California State Univ., Long Beach, CA

The author used two fixed-point TMS320C25 digital signal processors (DSPs) to implement in parallel the FFT. The significance of this multiprocessing system is: (1) the number of times block data transfer occurs between these two DSPs is minimum, (2) each DSP can independently perform the same FFT routine with different data set, and (3) the total computational load is nearly equally distributed to two DSPs. The speedup of this system over a single sequential processor is close to two

Published in:

Industrial Electronics, IEEE Transactions on  (Volume:41 ,  Issue: 1 )

Date of Publication:

Feb 1994

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.