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Fast parallel algorithm for ternary multiplication using multivalued I2L technology

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2 Author(s)
M. De ; Univ. Sci. Instrum. Centre, Kalyani Univ., India ; B. P. Sinha

Presents an algorithm for parallel multiplication of two n-bit ternary numbers. This algorithm uses the technique of column compression and computes the product in (2 upper bound [log2n]+2) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implementation. The same algorithm is also applicable to the multiplication of negative numbers

Published in:

IEEE Transactions on Computers  (Volume:43 ,  Issue: 5 )