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Standby/active mode logic for sub-1-V operating ULSI memory

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6 Author(s)
Takashima, D. ; ULSI Res. Center, Toshiba Corp., Kawasaki, Japan ; Watanabe, Shigeyoshi ; Nakano, H. ; Oowaki, Y.
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New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 4 )

Date of Publication:

Apr 1994

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