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250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

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9 Author(s)
Y. Takai ; LSI Memory Div., NEC Corp., Kanagawa, Japan ; M. Nagase ; M. Kitamura ; Y. Koshikawa
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A 3.3-V 512-k×18-b×2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm2, which is the same die size as the conventional DRAM, has been achieved with 0.50-μm CMOS process technology

Published in:

IEEE Journal of Solid-State Circuits  (Volume:29 ,  Issue: 4 )