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Design flow for the development of new FPGA architectures

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1 Author(s)
S. C. Beavis ; Pilkington Micro-Electron. Ltd., Cheshire, UK

Illustrates the design flow for a new generation of the dynamically programmable logic device (DPLD), but is also relevant to other technologies. The marketing and commercial phase involves evaluating and patent filing of features to be incorporated into a new generation of DPLD. This is presented to potential licensees and with further discussion results in an agreed target specification. The majority of the target specification for a new generation of DPLD is derived from experience of previous DPLD architectures and the licensee market and process requirements. Architectural and CAD features that have been previously analysed to achieve a required performance are re-used extensively. An example of this is the fine-grain DPLD core architecture which is now approaching its 4th generation

Published in:

Field Programmable Gate Arrays - Technology and Applications, IEE Colloquium on

Date of Conference:

15 Feb 1993