Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Neuron MOS winner-take-all circuit and its application to associative memory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yamashita, T. ; Tohoku Univ., Sandai, Japan ; Shibata, T. ; Ohmi, T.

An implementation of a winner-take-all circuit that is based on a neuron MOSFET, a transistor that simulates the function of biological neurons with a single device, is presented. A standard double-polysilicon CMOS process is used to implement an associative memory network in which the stored data set closest to the input data is selected. Even if the data stored in the associative memory do not exactly match the sample data, the circuit finds the closest data set using a vMOS winner-take-all circuit. The winner-take-all circuit containing two unit cells is shown. Experimental results demonstrating how the circuit determines the 'winner' and 'loser' are presented. Simulation results for the sorting circuit are also presented.<>

Published in:

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Date of Conference:

24-26 Feb. 1993