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Automatic impedance control

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3 Author(s)
DeHon, A. ; Artificial Intelligence Lab., MIT, Cambridge, MA, USA ; Knight, T., Jr. ; Simon, T.

The authors describe circuits and techniques that provide automatic on-chip impedance matching between a series-terminated, low-voltage swing, CMOS I/O pad, and an external interconnect. The automatic impedance control technique employs a digitally controlled output impedance driver, a high-gain, low-voltage differential receiver, and an IEEE-1149.1-1990 compatible test access port. The techniques presented here design circuits that compensate for external environmental variations. A component to test these circuits uses a 0.8- mu m effective gate-length process. The test components exhibit 2-ns I/O latencies with 1-ns rise/fall times and match impedances between 30 and 100 Omega .<>

Published in:

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Date of Conference:

24-26 Feb. 1993