By Topic

Modelling and performance analysis of digital baseband processor of the GPS receiver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Weihua Zhuang ; Dept. of Electr. Eng., Ottawa Univ., Ont., Canada ; K. M. Sundara Murthy

A global positioning system (GPS) receiver has been modelled and implemented in software. A digital full-time delay lock loop (DDLL) is designed for the pseudorange time delay measurement and a digital phase-locked loop (DPLL) is applied for measurements of the carrier beat phase and Doppler shift. The closed form expressions of the detection and false-alarm probabilities for the code phase acquisition process and the variance of the code phase tracking error for the code phase fine synchronization process are derived. The performance of the modelled static receivers is validated by computer simulations

Published in:

Personal, Indoor and Mobile Radio Communications, 1992. Proceedings, PIMRC '92., Third IEEE International Symposium on

Date of Conference:

19-21 Oct 1992