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Testability challenges to achieve zero defect goal in MCM manufacturing

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2 Author(s)
D. F. McQueeney ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; T. J. Zittritsch

Discusses some approaches to chip test and MCM (multi-chip module) assembly, and describes a module designed for CMOS logic, including details of its chip attach technology, test, and burn-in strategy. It is concluded that test procedures can be more easily implemented if the chips are designed for an MCM environment. Two significant challenges are the use on an MCM of chips whose design did not consider MCM test issues, and modules made up of chips from different manufacturers

Published in:

Electronics Manufacturing Technology Symposium, 1991., Eleventh IEEE/CHMT International

Date of Conference:

16-18 Sep 1991