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A data-parallel programming model for reconfigurable architectures

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2 Author(s)
Guccione, S.A. ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; Gonzalez, M.J., Jr.

Recently, several machines have been built using field programmable gate array (FPGA) technology. These reconfigurable architectures have demonstrated very high performance for a variety of problems. The configuration of these machines typically rely on some form of hardware specification. The authors demonstrate that a more traditional software approach may be used. A vector based data-parallel model and its mapping to a reconfigurable architecture are introduced. Included in the model are parallel prefix or scan operators. The language supporting this model is a subset of the C programming language

Published in:

FPGAs for Custom Computing Machines, 1993. Proceedings. IEEE Workshop on

Date of Conference:

5-7 Apr 1993