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Zero skew clock routing in multiple-clock synchronous systems

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3 Author(s)
Khan, W. ; Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA ; Hossain, M. ; Sherwani, N.

A clock routing algorithm for two-phase clock systems is presented. The algorithm, which minimizes both intraclock skew and interclock skew, has been implemented on SPARC 1+ in C and has been tested on several industrial benchmarks as well as on randomly generated examples. In particular, the result was tested for a 267 synchronous component circuit at clock rates of 100 MHz. It is significant that this is the first ever result which deals with multiple clock routing with zero skew.<>

Published in:

Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on

Date of Conference:

8-12 Nov. 1992