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Automatic gate-level synthesis of speed-independent circuits

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2 Author(s)
Beerel, P.A. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Meng, T.H.-Y.

A CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates is presented. The synthesized circuits are speed-independent-that is, they work correctly regardless of individual gate delays. Synthesis results for a variety of specifications taken from industry and previously published examples are presented. The speed-independent circuits are compared with those non-speed-independent circuits synthesized using previously described algorithms, in which delay elements are added to remove circuit hazards. These synthesis results show that the new circuits are on average approximately 25% faster with an area penalty of only 15%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efficient circuits compared to those synthesized with timing constraints.<>

Published in:

Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on

Date of Conference:

8-12 Nov. 1992