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Hot-carrier-reliability design guidelines for CMOS logic circuits

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5 Author(s)
K. N. Quader ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; E. R. Minami ; Wei-Jen Ko ; P. K. Ko
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Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ftrise and 10/ftfall respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively

Published in:

IEEE Journal of Solid-State Circuits  (Volume:29 ,  Issue: 3 )