Referenced Items are not available for this document.
A mixed-signal, 7.0 Mbyte/s PRML (partial-response maximum likelihood) read/write channel is discussed in this paper. PR-IV (minimum signal bandwidth) for signal encoding is used, along with ML (maximum likelihood) detection to achieve superior error rate performance. Signal equalization is provided using a programmable ten-tap FIR (finite impulse response) digital filter. This read/write channel is implemented on a single chip using analog circuits and 20 K CMOS logic gates. The 7.5 mm square chip uses a 5 V, 1 μm, BiCMOS process with a 6 GHz n-p-n and a 1 GHz p-n-p and is packaged in a 100-lead metal QFPK (quad flat pack)
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:29
,
Issue:
3
)
Date of Publication: Mar 1994
- Page(s):
- 177 - 184
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 4684145
- Digital Object Identifier :
- 10.1109/4.278338
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Mar 1994
- Sponsored by :
- IEEE Solid-State Circuits Society
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