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Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology

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3 Author(s)
Schlag, M. ; Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA ; Chan, P.K. ; Kong, J.

The performance of multilevel logic minimization tools for a lookup-table-based field-programmable gate array (FPGA) technology was examined. The experiments used the university tools, misII for combinational logic minimization and mustang for state assignments, and the industrial tools xnfmap for technology mapping and apr for automatic placement and routing. The quality of the multilevel logic minimization tools was measured by the number of routed configurable logic blocks (CLBs) in the FPGA realization. A linear relationship between the number of literals and the number of routed CLBs was found. In all 34 MCNC-89 benchmark finite state machines, one-hot state assignment resulted in substantially fewer CLBs than any other state encoding methods available in mustang. A delay model that provides routing delay prediction based on fan-out is presented and used to estimate the delays of the FPGA implementation of logic expressions prior to technology mapping, place, and route

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 5 )