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Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis

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4 Author(s)
S. Malik ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; K. J. Singh ; R. K. Brayton ; A. Sangiovanni-Vincentelli

The problem of minimizing the cycle time of a given pipelined circuit is considered. The idea of simultaneous retiming and resynthesis is used to optimize a pipelined circuit to meet a given cycle time. An instance of the pipelined cycle optimization problem is specified by the circuit, a set of input arrival times relative to the clock, a set of required output times relative to the clock, and a given cycle time that it must meet. Given the instance of the pipelined performance optimization problem, the authors construct an instance of a combinational speedup problem. This is specified by a combinational logic circuit, a set of arrival times on the inputs, and a set of required times for the outputs which must be met. A constructive proof that the pipelined problem has a solution if and only if the combinational problem has a solution is given. This result shows that it is enough to consider only the combinational speedup problem, and all known techniques for that can be directly applied to generate a solution for the pipelined problem

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:12 ,  Issue: 5 )