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Hardware implementation of Montgomery's modular multiplication algorithm

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2 Author(s)
Eldridge, S.E. ; Comput. Dept., Univ. of Manchester Inst. of Sci. & Technol., Manchester, UK ; Walter, C.D.

Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic

Published in:

Computers, IEEE Transactions on  (Volume:42 ,  Issue: 6 )

Date of Publication:

Jun 1993

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