By Topic

An ATM queue manager with multiple delay and loss priorities

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chao, H.J. ; Polytech. Univ., New York, NY, USA ; Uzun, N.

The performances in cell loss, queuing delay, and standard deviation of four different service classes at the output queue on an asynchronous transfer mode (ATM) output-buffered switch are evaluated. An implementation architecture for the queue manager is proposed. The architecture allows all service classes to share the buffer until the buffer is filled up, and then cells with the lowest loss priority start to be discarded, i.e., the so-called push out scheme. The implementation architecture applies the concepts of fully distributed and highly parallel processing. to schedule the cells' departing or discarding sequence. An implemented VLSI sequencer chip can be used to realize a queue manager that deals with multiple delay and loss priorities

Published in:

Global Telecommunications Conference, 1992. Conference Record., GLOBECOM '92. Communication for Global Users., IEEE

Date of Conference:

6-9 Dec 1992