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Distributed VLSI simulation on a network of workstations

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2 Author(s)
Karthik, S. ; Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA ; Abraham, J.A.

Switch level simulation has been mapped to a distributed platform using a network of workstations. Model parallelism is used with preprocessing to partition the circuit to be simulated among the processors. A high-level pipelining scheme with multiple buffers is proposed to overcome the effects of a low-bandwidth network. Speedups of up to 4.1 with five processors have been obtained for medium sized ISCAS benchmark circuits. The speedups achieved using distributed simulation are very close to those obtained with the same switch-level simulator implemented on a shared-memory parallel machine

Published in:

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Date of Conference:

11-14 Oct 1992

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