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Delay prediction for technology-independent logic equations

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3 Author(s)
P. T. Gutwin ; EECS Dept., California Univ., Berkeley, CA, USA ; P. C. McGeer ; R. K. Brayton

A technology-independent delay model is introduced. This model assumes that the technology mapper will attempt modest local restructuring of the network. It models the restructuring by producing a staggered network for each gate based on the arrival times of the fan-in signals. The delay of the network is calculated using the staggered network, and when compared to the delay reported by technology mapping, is found to be accurate and efficiently obtained

Published in:

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Date of Conference:

11-14 Oct 1992