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Constraint solving for test case generation: a technique for high-level design verification

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2 Author(s)
A. K. Chandra ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; V. S. Iyengar

The use of constraint solving and symbolic execution to generate highly probing test cases is discussed. A system called AVPGEN, which uses such techniques for debugging high-level machine designs and has already proved useful in finding errors, is described. AVPGEN generates large numbers of architecture verification programs. It consists of a generator and a symbolic simulator. The generator uses constraint solving, symbolic values and undo capabilities to set up conditions. These conditions may be architecture specific or design specific. The simulator in AVPGEN, although not bug-free, is considerably simpler than any of the hardware implementations it is used to verify

Published in:

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Date of Conference:

11-14 Oct 1992