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The architecture of the LR33020 graphX processor: a MIPS-RISC based X-terminal controller

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1 Author(s)
Desai, S. ; LSI Logic Corp., Milpitas, CA, USA

The architecture and implementation of a MIPS-RISC-based application-specific microprocessor designed specifically for X-Window terminals is described. It consists of a graphics coprocessor integrated with a MIPS-1 (R3000)-compatible CPU core along with system-level functions found in a typical X-Terminal. The design of the graphics coprocessor has been optimized for accelerating low-level graphics operations typical in X-Windows applications. It is implemented as coprocessor 2. A set of coprocessor 2 graphics instructions process pixel data fetched by dedicated DMA channels through a high-bandwidth (64 b) memory interface. The combination of the graphics coprocessor and high-bandwidth memory interface result in a very high performance. The presence of system-level functions on the same die as the CPU and graphics engine make for a very highly integrated processor

Published in:

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Date of Conference:

11-14 Oct 1992

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